The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2013
Filed:
Dec. 15, 2010
Xinhong Cheng, Shanghai, CN;
Dawei He, Shanghai, CN;
Zhongjian Wang, Shanghai, CN;
Dawei Xu, Shanghai, CN;
Chao Xia, Shanghai, CN;
Zhaorui Song, Shanghai, CN;
Yuehui Yu, Shanghai, CN;
Xinhong Cheng, Shanghai, CN;
Dawei He, Shanghai, CN;
Zhongjian Wang, Shanghai, CN;
Dawei Xu, Shanghai, CN;
Chao Xia, Shanghai, CN;
Zhaorui Song, Shanghai, CN;
Yuehui Yu, Shanghai, CN;
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Changning District, Shanghai, CN;
Abstract
The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer. The present invention is capable of releasing the charge accumulated at the lower interface of the BOX layer, eliminating the effect of the vertical charge on the charge balance between the p-type pillar and the n-type pillar, and therefore completely eliminating the substrate-assisted depletion effects and elevating the breakdown voltage of the device.