The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8354327 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 15, 2013

Filed:

Apr. 21, 2011
Applicants:

Chen Zengxiang, Singapore, SG;

Zhao Feng, Shanghai, CN;

Liu Huang, Singapore, SG;

Yuan Shaoning, Singapore, SG;

Inventors:

Chen Zengxiang, Singapore, SG;

Zhao Feng, Shanghai, CN;

Liu Huang, Singapore, SG;

Yuan Shaoning, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.


Find Patent Forward Citations

Zengxiang, Chen. (2013). Scheme for planarizing through-silicon vias (U.S. Patent No. 8354327). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8354327

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