The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2013

Filed:

Oct. 07, 2010
Applicants:

Satoshi Itaya, Tokyo, JP;

Kayoko Shibata, Tokyo, JP;

Shoji Azuma, Tokyo, JP;

Akira Ide, Tokyo, JP;

Inventors:

Satoshi Itaya, Tokyo, JP;

Kayoko Shibata, Tokyo, JP;

Shoji Azuma, Tokyo, JP;

Akira Ide, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.


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