The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2013
Filed:
Jan. 29, 2010
Bei Zhu, Los Gatos, CA (US);
Hong-tze Pan, Cupertino, CA (US);
Bang-thu Nguyen, Santa Clara, CA (US);
Qi Lin, Cupertino, CA (US);
Zhiyuan Wu, San Jose, CA (US);
Ping-chin Yeh, San Jose, CA (US);
Jae-gyung Ahn, Pleasanton, CA (US);
Yun Wu, San Jose, CA (US);
Bei Zhu, Los Gatos, CA (US);
Hong-Tze Pan, Cupertino, CA (US);
Bang-Thu Nguyen, Santa Clara, CA (US);
Qi Lin, Cupertino, CA (US);
Zhiyuan Wu, San Jose, CA (US);
Ping-Chin Yeh, San Jose, CA (US);
Jae-Gyung Ahn, Pleasanton, CA (US);
Yun Wu, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An integrated circuit ('IC') fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.