The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2013

Filed:

Dec. 11, 2007
Applicants:

Amir Alon, Ramat Tshai, IL;

David Goren, Nesher, IL;

Rachel Gordin, Hadera, IL;

Betty Livshitz, Qiriat, IL;

Sherman Anatoly, Haifa, IL;

Michael Zelikson, Haifa, IL;

Inventors:

Amir Alon, Ramat Tshai, IL;

David Goren, Nesher, IL;

Rachel Gordin, Hadera, IL;

Betty Livshitz, Qiriat, IL;

Sherman Anatoly, Haifa, IL;

Michael Zelikson, Haifa, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.


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