The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2013
Filed:
May. 16, 2008
Serafino Bueti, Waterbury, VT (US);
Kenneth Joseph Goodnow, Essex Junction, VT (US);
Todd Edwin Leonard, Williston, VT (US);
Gregory John Mann, Wheaton, IL (US);
Jason Michael Norman, Essex Junction, VT (US);
Clarence Rosser Ogilvie, Huntington, VT (US);
Peter Anthony Sandon, Essex Junction, VT (US);
Charles S. Woodruff, Charlotte, VT (US);
Serafino Bueti, Waterbury, VT (US);
Kenneth Joseph Goodnow, Essex Junction, VT (US);
Todd Edwin Leonard, Williston, VT (US);
Gregory John Mann, Wheaton, IL (US);
Jason Michael Norman, Essex Junction, VT (US);
Clarence Rosser Ogilvie, Huntington, VT (US);
Peter Anthony Sandon, Essex Junction, VT (US);
Charles S. Woodruff, Charlotte, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.