Process for dithering a time to digital converter and circuits for performing said process

Abstract

A process inserts a random noise in a Time to Digital Converter (TDC) designed for calculating the phase error between a first high frequency signal Fwith respect to a second reference signal, switching at a lower frequency. The process involves: processing of the first signal Fby using a chain of delays having a set of n elementary delays which number is chosen so as to extend over a full period of the first signal; storing the outputs of the chain of delays in a set of latches and generation of a thermometer code presenting a stream of '1' separated from a stream of '0' by a border corresponding to the transition of the first signal with respect to the second reference signal; reducing the thermometer code by a random number PN of bits; processing of the result in an edge detecting and thermometer code decoding so as to generate two variables Δtand Δtwhich are representative of the difference between the rise and fall time of the first signal with respect to the second reference signal; computing the normalized gain so as to generate an average value of 1/T; adding to the value Δta binary value corresponding to the number of bits PN; multiplying the preceding result by the average value of 1/Tand computing the phase error between the signals. The delay chain may be arranged with inverters. The process is particularly but not exclusively useful for carrying out a TDC convertor for the purpose of synthesizing of frequencies.