The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2013

Filed:

Aug. 29, 2007
Applicants:

Neil Mclellan, Toronto, CA;

Adam Zbrzezny, Scarborough, CA;

Inventors:

Neil Mclellan, Toronto, CA;

Adam Zbrzezny, Scarborough, CA;

Assignee:

ATI Technologies ULC, Markham, Ontario, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.


Find Patent Forward Citations

Mclellan, Neil. (2013). Wafer level packaging of semiconductor chips (U.S. Patent No. 8344505). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8344505

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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