The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2013
Filed:
Aug. 10, 2007
Steven C. Bird, San Jose, CA (US);
Linda M. Mazaheri, Los Gatos, CA (US);
Bob Needham, San Jose, CA (US);
Phuong Rosalynn Duong, San Jose, CA (US);
Steven C. Bird, San Jose, CA (US);
Linda M. Mazaheri, Los Gatos, CA (US);
Bob Needham, San Jose, CA (US);
Phuong Rosalynn Duong, San Jose, CA (US);
Cisco Technology, Inc., San Jose, CA (US);
Abstract
Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.