The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2012
Filed:
Jan. 14, 2009
Ji-hwan Hwang, Asan-si, KR;
Dong-han Kim, Osan-si, KR;
Chul-woo Kim, Cheonan-si, KR;
Chung-ye Chung, Hwaseong-si, KR;
Kwang-jin Bae, Asan-si, KR;
Ji-Hwan Hwang, Asan-si, KR;
Dong-Han Kim, Osan-si, KR;
Chul-Woo Kim, Cheonan-si, KR;
Chung-Ye Chung, Hwaseong-si, KR;
Kwang-Jin Bae, Asan-si, KR;
SAMSUNG Electronics Co., Ltd., Suwon-si, KR;
Abstract
A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip.