The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2012

Filed:

Aug. 16, 2010
Applicants:

Nan-hsin Tseng, Shanhua Township, TW;

Chin-chou Liu, Jhubei, TW;

Wei-pin Changchien, Taichung, TW;

Kin Lam Tong, Hsin-Chu, TW;

Inventors:

Nan-Hsin Tseng, Shanhua Township, TW;

Chin-Chou Liu, Jhubei, TW;

Wei-Pin Changchien, Taichung, TW;

Kin Lam Tong, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/23 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.


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