The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2012

Filed:

May. 09, 2011
Applicants:

Dixie Dunn, Salt Lake City, UT (US);

Paul Thorup, West Jordan, UT (US);

Dean E. Probst, West Jordan, UT (US);

Michael D. Gruenhagen, Salt Lake City, UT (US);

Inventors:

Dixie Dunn, Salt Lake City, UT (US);

Paul Thorup, West Jordan, UT (US);

Dean E. Probst, West Jordan, UT (US);

Michael D. Gruenhagen, Salt Lake City, UT (US);

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.


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