The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2012
Filed:
Mar. 30, 2011
Abhishek Dube, Fishkill, NY (US);
Viorel Ontalus, Danbury, CT (US);
Kathryn T. Schonenberg, Wappingers Falls, NY (US);
Zhengmao Zhu, Poughkeepsie, NY (US);
Abhishek Dube, Fishkill, NY (US);
Viorel Ontalus, Danbury, CT (US);
Kathryn T. Schonenberg, Wappingers Falls, NY (US);
Zhengmao Zhu, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.