The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2012

Filed:

Mar. 09, 2010
Applicants:

Tadashi Yamaguchi, Tokyo, JP;

Toshiaki Tsutsumi, Tokyo, JP;

Satoshi Ogino, Tokyo, JP;

Kazumasa Yonekura, Tokyo, JP;

Kenji Kawai, Tokyo, JP;

Yoshihiro Miyagawa, Tokyo, JP;

Tomonori Okudaira, Tokyo, JP;

Keiichiro Kashihara, Tokyo, JP;

Kotaro Kihara, Itami, JP;

Inventors:

Tadashi Yamaguchi, Tokyo, JP;

Toshiaki Tsutsumi, Tokyo, JP;

Satoshi Ogino, Tokyo, JP;

Kazumasa Yonekura, Tokyo, JP;

Kenji Kawai, Tokyo, JP;

Yoshihiro Miyagawa, Tokyo, JP;

Tomonori Okudaira, Tokyo, JP;

Keiichiro Kashihara, Tokyo, JP;

Kotaro Kihara, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

To improve the performance of semiconductor devices. Over an n-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.


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