The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2012

Filed:

Jul. 27, 2006
Applicants:

Baik-woo Lee, Atlanta, GA (US);

Chong Yoon, Roswell, GA (US);

Verkatesh Sundaram, Atlanta, GA (US);

Rao Tummala, Stone Mountain, GA (US);

Inventors:

Baik-Woo Lee, Atlanta, GA (US);

Chong Yoon, Roswell, GA (US);

Verkatesh Sundaram, Atlanta, GA (US);

Rao Tummala, Stone Mountain, GA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are any electronic system or module which includes embedded actives and discrete passives, and methods for use in fabricating packages containing embedded active devices and/or discrete passive devices. Exemplary apparatus comprises a plurality of build-up layers defining circuit interconnections and that comprise one or more thin film type of embedded passive devices, at least a cavity formed in the build-up layers, and at least an active device and/or at least a discrete passive device disposed in the cavity and electrically connected to the circuit interconnections of the build-up layers. A stiffener may be coupled to an exposed (back) surface of the active device and to an adjacent surface of the build-up layers. The build-up layers may be mounted to a core, and the core may be attached to a printed circuit board. Alternatively, a bottom surface of the build-up layers may be mounted to a printed circuit board without core. The packages have a chip reworkability, an easier thermal management, a very thin profile and enhanced electrical performance comparable to packages produced using chip-first or chip-middle approaches.


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