The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2012
Filed:
Jul. 08, 2010
Applicant:
Sreemala Pannala, San Diego, CA (US);
Inventor:
Sreemala Pannala, San Diego, CA (US);
Assignee:
Oracle America, Inc., Redwood City, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip.
Pannala, Sreemala. (2012). Package designs for fully functional and partially functional chips (U.S. Patent No. 8332791). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8332791
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile