The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Jun. 23, 2005
Applicants:

James Akiyama, Beaverton, OR (US);

William H. Clifford, Gig Harbor, WA (US);

Paul M. Brown, University Place, WA (US);

Inventors:

James Akiyama, Beaverton, OR (US);

William H. Clifford, Gig Harbor, WA (US);

Paul M. Brown, University Place, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic, a reorder table and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The reorder table includes two or more table elements. Each table element includes a shared address component and an independent address component corresponding to each of the two or more independently addressable subchannels. The transaction assembler combines the shared and independent address components in a reorder table element and issue a single memory transaction.


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