The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Nov. 27, 2008
Applicants:

Phanimithra Gangalakurti, Hyderabad, IN;

Karthik Vaidyanathan, San Jose, CA (US);

Partha Sarathy Murali, San Jose, CA (US);

Indusheknar Ayyalasomayajula, Hyderabad, IN;

Inventors:

Phanimithra Gangalakurti, Hyderabad, IN;

Karthik Vaidyanathan, San Jose, CA (US);

Partha Sarathy Murali, San Jose, CA (US);

InduSheknar Ayyalasomayajula, Hyderabad, IN;

Assignee:

Redpine Signals, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); G06F 17/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.


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