The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

May. 18, 2010
Applicants:

Won-joon Choi, Gyeonggi-do, KR;

Moon-sig Joo, Gyeonggi-do, KR;

Ki-hong Lee, Gyeonggi-do, KR;

Beom-yong Kim, Gyeonggi-do, KR;

Jun-yeol Cho, Gyeonggi-do, KR;

Young-wook Lee, Gyeonggi-do, KR;

Inventors:

Won-Joon Choi, Gyeonggi-do, KR;

Moon-Sig Joo, Gyeonggi-do, KR;

Ki-Hong Lee, Gyeonggi-do, KR;

Beom-Yong Kim, Gyeonggi-do, KR;

Jun-Yeol Cho, Gyeonggi-do, KR;

Young-Wook Lee, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor, Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction.


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