The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2012
Filed:
May. 03, 2010
Jae-gyung Ahn, Pleasanton, CA (US);
Myongseob Kim, Pleasanton, CA (US);
Ping-chin Yeh, San Jose, CA (US);
Zhiyuan Wu, San Jose, CA (US);
John Cooksey, Brentwood, CA (US);
Jae-Gyung Ahn, Pleasanton, CA (US);
Myongseob Kim, Pleasanton, CA (US);
Ping-Chin Yeh, San Jose, CA (US);
Zhiyuan Wu, San Jose, CA (US);
John Cooksey, Brentwood, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.