The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2012
Filed:
Sep. 17, 2010
Man Hua Chen, Shanghai, CN;
Lien Hung Cheng, Shanghai, CN;
Man Hua Chen, Shanghai, CN;
Lien Hung Cheng, Shanghai, CN;
Abstract
A method for fabricating an integrated circuit device includes providing a semiconductor substrate having a first region and a second region, e.g., peripheral region. The method forms a stop layer overlying the first and second regions and a low k dielectric layer (e.g., k<2.9) overlying the stop layer in the first and second regions. The method forms a cap layer overlying the low k dielectric layer. In an embodiment, the method initiates formation of a plurality of via structures within a first portion of the low k dielectric layer overlying the first region and simultaneously initiates formation of an isolated via structure for in the second region of the semiconductor substrate, using one or more etching processes. The method includes ceasing formation of the plurality of via structures within the first portion and ceasing formation of the isolated via structure in the second region when one or more portions of stop layer have been exposed.