The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Dec. 18, 2009
Applicants:

Byoung-kyu Lee, Suwon-si, KR;

Se-jin Chung, Yongin-si, KR;

Byoung-june Kim, Seoul, KR;

Czang-ho Lee, Hwaseong-si, KR;

Myung-hun Shin, Suwon-si, KR;

Min-seok OH, Yongin-si, KR;

Ku-hyun Kang, Suwon-si, KR;

Yuk-hyun Nam, Goyang-si, KR;

Seung-jae Jung, Seoul, KR;

Min Park, Seoul, KR;

Mi-hwa Lim, Chungeheongnam-do, KR;

Joon-young Seo, Seoul, KR;

Inventors:

Byoung-Kyu Lee, Suwon-si, KR;

Se-Jin Chung, Yongin-si, KR;

Byoung-June Kim, Seoul, KR;

Czang-Ho Lee, Hwaseong-si, KR;

Myung-Hun Shin, Suwon-si, KR;

Min-Seok Oh, Yongin-si, KR;

Ku-Hyun Kang, Suwon-si, KR;

Yuk-Hyun Nam, Goyang-si, KR;

Seung-Jae Jung, Seoul, KR;

Min Park, Seoul, KR;

Mi-Hwa Lim, Chungeheongnam-do, KR;

Joon-Young Seo, Seoul, KR;

Assignees:

Samsung Display Co., Ltd., Yongin, Gyeonggi-do, KR;

Samsung SDI Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a method of manufacturing a photovoltaic device using a Joule heating-induced crystallization method. The method includes: forming a first conductive pattern on a substrate; forming a photoelectric conversion layer on the substrate having the first conductive pattern; and crystallizing at least part of the photoelectric conversion layer by applying an electric field to the photoelectric conversion layer, wherein the photoelectric conversion layer includes a first amorphous semiconductor layer containing first impurities, a second intrinsic, amorphous semiconductor layer, and a third amorphous semiconductor layer containing second impurities.


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