The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2012
Filed:
May. 27, 2008
Chien-shao Tang, Hsin-Chu, TW;
Dah-chuen Ho, Taichung, TW;
Yu-chang Jong, Hsin-Chu, TW;
Zhe-yi Wang, Hsin-Chu, TW;
Yuh-hwa Chang, Shulin, TW;
Yogendra Yadav, Hsin-Chu, TW;
Chien-Shao Tang, Hsin-Chu, TW;
Dah-Chuen Ho, Taichung, TW;
Yu-Chang Jong, Hsin-Chu, TW;
Zhe-Yi Wang, Hsin-Chu, TW;
Yuh-Hwa Chang, Shulin, TW;
Yogendra Yadav, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.