The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2012

Filed:

Oct. 24, 2011
Applicants:

Jonghae Kim, Fishkill, NY (US);

Shiqun Gu, San Diego, CA (US);

Brian Matthew Henderson, Escondido, CA (US);

Thomas R. Toms, Dripping Springs, TX (US);

Matthew Nowak, San Diego, CA (US);

Inventors:

Jonghae Kim, Fishkill, NY (US);

Shiqun Gu, San Diego, CA (US);

Brian Matthew Henderson, Escondido, CA (US);

Thomas R. Toms, Dripping Springs, TX (US);

Matthew Nowak, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.


Find Patent Forward Citations

Kim, Jonghae. (2012). Techniques for placement of active and passive devices within a chip (U.S. Patent No. 8324066). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8324066

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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