The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8318548 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 27, 2012

Filed:

Aug. 10, 2010
Applicants:

Kunihiro Yamashita, Kanagawa, JP;

Kazushi Hatauchi, Kanagawa, JP;

Tetsuya Uebayashi, Kanagawa, JP;

Inventors:

Kunihiro Yamashita, Kanagawa, JP;

Kazushi Hatauchi, Kanagawa, JP;

Tetsuya Uebayashi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high positional accuracy of a semiconductor chip is attained to stabilize the quality of a semiconductor device. In a die bonding process during assembly of an SIP, a microcomputer chip not required to have a high positional accuracy is picked up with a surface non-contact type collet and is die-bonded onto a first chip mounting portion, thereafter, an ASIC chip required to have a high positional accuracy is picked up with a surface contact type collet and die-bonded onto a second chip mounting portion. By thus using two types of collets properly, not only a high positional accuracy of the ASIC chip which has been die-bonded with the surface contact type collet is attained, but also the quality of the SIP is stabilized.


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