The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2012
Filed:
Jun. 02, 2010
Taranjit Kukal, Delhi, IN;
Chris Cheung, Westford, MA (US);
Vikas Kohli, Noida, IN;
Keith Felton, Sterling, MA (US);
Frank X. Farmar, Amherst, NH (US);
Steven R. Durrill, Campbell, CA (US);
Taranjit Kukal, Delhi, IN;
Chris Cheung, Westford, MA (US);
Vikas Kohli, Noida, IN;
Keith Felton, Sterling, MA (US);
Frank X. Farmar, Amherst, NH (US);
Steven R. Durrill, Campbell, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method of interconnecting a first plurality of electronic components and a second plurality of electronic components to form an electronic circuit includes exporting a first netlist representing a first interconnection of the first electronic components in a first design entry tool, exporting a second netlist representing a second interconnection of the second electronic components in a second design entry tool, providing at least a first interface from the second plurality to the first plurality in the second design entry tool, populating the first interface through the first design entry tool, and exporting a third netlist representing the first interface from the second plurality to the first plurality from the second design entry tool, wherein the third netlist stitches the first netlist to the second netlist.