The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2012
Filed:
Jan. 28, 2010
Mahesh A. Iyer, Fremont, CA (US);
Sudipto Kundu, Sunnyvale, CA (US);
Mahesh A. Iyer, Fremont, CA (US);
Sudipto Kundu, Sunnyvale, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate.