The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2012
Filed:
Mar. 05, 2010
Gitu Jain, Los Gatos, CA (US);
Vinay Verma, Fremont, CA (US);
Taneem Ahmed, Toronto, CA;
Sandor S. Kalman, Santa Clara, CA (US);
Sanjeev Kwatra, Cupertino, CA (US);
Christopher H. Kingsley, Longmont, CO (US);
Jason H. Anderson, Toronto, CA;
Satyaki Das, San Jose, CA (US);
Gitu Jain, Los Gatos, CA (US);
Vinay Verma, Fremont, CA (US);
Taneem Ahmed, Toronto, CA;
Sandor S. Kalman, Santa Clara, CA (US);
Sanjeev Kwatra, Cupertino, CA (US);
Christopher H. Kingsley, Longmont, CO (US);
Jason H. Anderson, Toronto, CA;
Satyaki Das, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.