The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2012

Filed:

Sep. 17, 2010
Applicants:

Joel K. W. Yang, Research Link, SG;

Karl K. Berggren, Delft, NL;

Yeon Sik Jung, Cambridge, MA (US);

Caroline A. Ross, Arlington, MA (US);

Inventors:

Joel K. W. Yang, Research Link, SG;

Karl K. Berggren, Delft, NL;

Yeon Sik Jung, Cambridge, MA (US);

Caroline A. Ross, Arlington, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 1/50 (2012.01); H01L 21/31 (2006.01); H01L 21/469 (2006.01);
U.S. Cl.
CPC ...
Abstract

Complex self-assembled patterns can be created using a sparse template and local changes to the shape or distribution of the posts of the template to direct pattern generation of block copolymer. The post spacing in the template is formed commensurate with the equilibrium periodicity of the block copolymer, which controls the orientation of the linear features. Further, the posts can be arranged such that the template occupies only a few percent of the area of the final self-assembled patterns. Local aperiodic features can be introduced by changing the period or motif of the lattice or by adding guiding posts. According to one embodiment, an array of carefully spaced and shaped posts, prepared by electron-beam patterning of an inorganic resist, can be used to template complex patterns in a cylindrical-morphology block copolymer. These complex self-assembled patterns can form a mask used in fabrication processes of arbitrary structures such as interconnect layouts.


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