The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8305791 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 06, 2012

Filed:

May. 20, 2010
Applicants:

Ching-wei Wu, Caotun, TW;

Cheng Hung Lee, Hsinchu, TW;

Li-chen Chen, Taipei, TW;

Weiyang Jiang, Zhejiang, CN;

Inventors:

Ching-Wei Wu, Caotun, TW;

Cheng Hung Lee, Hsinchu, TW;

Li-Chen Chen, Taipei, TW;

Weiyang Jiang, Zhejiang, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.


Find Patent Forward Citations

Wu, Ching-Wei. (2012). Memory circuit having memory cells with common source/drain region electrically isolated from all bit lines, system, and fabrication method thereof (U.S. Patent No. 8305791). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8305791

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