The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2012

Filed:

Dec. 02, 2011
Applicants:

Ravi Kurlagunda, Fremont, CA (US);

Ravi Sunkavalli, Milpitas, CA (US);

Vijay Bantval, Cherry Hill, NJ (US);

Rahul Nimaiyar, Sunnyvale, CA (US);

Inventors:

Ravi Kurlagunda, Fremont, CA (US);

Ravi Sunkavalli, Milpitas, CA (US);

Vijay Bantval, Cherry Hill, NJ (US);

Rahul Nimaiyar, Sunnyvale, CA (US);

Assignee:

Achronix Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.


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