The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2012

Filed:

Mar. 12, 2009
Applicants:

Hiroshi Watanabe, Tokyo, JP;

Naoki Yutani, Tokyo, JP;

Kenichi Ohtsuka, Tokyo, JP;

Kenichi Kuroda, Tokyo, JP;

Masayuki Imaizumi, Tokyo, JP;

Yoshinori Matsuno, Tokyo, JP;

Inventors:

Hiroshi Watanabe, Tokyo, JP;

Naoki Yutani, Tokyo, JP;

Kenichi Ohtsuka, Tokyo, JP;

Kenichi Kuroda, Tokyo, JP;

Masayuki Imaizumi, Tokyo, JP;

Yoshinori Matsuno, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an ntype semiconductor layer formed on an ntype semiconductor substrate; a first electrode that is formed on the ntype semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the ntype semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the ntype semiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the ntype semiconductor substrate.


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