Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants

Abstract

An insulated-gate field-effect transistor () provided along an upper surface of a semiconductor body contains a pair of source/drain zones (and) laterally separated by a channel zone (). A gate electrode () overlies a gate dielectric layer () above the channel zone. Each source/drain zone includes a main portion (M orM) and a more lightly doped lateral extension (E orE) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.