The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2012

Filed:

Apr. 05, 2011
Applicants:

Mark a Gerber, Lucas, TX (US);

David N Walter, Dallas, TX (US);

Inventors:

Mark A Gerber, Lucas, TX (US);

David N Walter, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device with a sheet-like insulating substrate () integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads () in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures () at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material () to contact the pads. Metal-filled surface grooves () in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.


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