The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2012

Filed:

Sep. 26, 2008
Applicants:

Keith Bowman, Hillsboro, OR (US);

James Tachanz, Portland, OR (US);

Nam Sung Kim, El Dorado Hills, CA (US);

Janice Lee, Fremont, CA (US);

Chris Wilkerson, Portland, OR (US);

Shih-lien L. LU, Portland, OR (US);

Tanay Karnlk, Portland, OR (US);

Vivek DE, Beaverton, OR (US);

Inventors:

Keith Bowman, Hillsboro, OR (US);

James Tachanz, Portland, OR (US);

Nam Sung Kim, El Dorado Hills, CA (US);

Janice Lee, Fremont, CA (US);

Chris Wilkerson, Portland, OR (US);

Shih-Lien L. Lu, Portland, OR (US);

Tanay Karnlk, Portland, OR (US);

Vivek De, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/33 (2006.01); H03M 13/01 (2006.01);
U.S. Cl.
CPC ...
Abstract

Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.


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