Synchronising between clock domains

Abstract

An integrated circuitis provided with multiple clock domains separated by a clock boundary. Data values are passed across the clock boundaryusing a first-in-first-out memory (FIFO), a read pointer and a write pointer for the FIFO are passed across the clock boundaryand must be synchronized to the receiving clock frequency. The clocks being used on either side of the clock boundarymay be switched and have a variable relationship therebetween. Multiple synchronization paths are provided within pointer synchronizing circuitrywhich are used depending upon the particular relationship between the clocks on either side of the clock boundary. A pre-switch pointer value is held in a transition registeruntil a post-switch pointer value is available from the new synchronizing pathwhen a switch in clock mode is made which requires an increase in synchronization delay.