The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2012

Filed:

Nov. 18, 2010
Applicants:

Tae Sik Yun, Ichon-shi, KR;

Hyung Dong Lee, Ichon-shi, KR;

Jun Gi Choi, Ichon-shi, KR;

Sang Jin Byeon, Ichon-shi, KR;

Sang Hoon Shin, Ichon-shi, KR;

Inventors:

Tae Sik Yun, Ichon-shi, KR;

Hyung Dong Lee, Ichon-shi, KR;

Jun Gi Choi, Ichon-shi, KR;

Sang Jin Byeon, Ichon-shi, KR;

Sang Hoon Shin, Ichon-shi, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 8/16 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.


Find Patent Forward Citations

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Yun, Tae. (2012). Semiconductor memory apparatus and test method thereof (U.S. Patent No. 8300496). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8300496

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