Methods and systems related to a configurable delay counter used with variable frequency clocks

Abstract

In certain arrangements and methods, a reset-able counter () produces multiple delay times as required by, for example, a finite state machine. The counter () counts a stored value by a configurable amount. That configurable amount is determined based upon the period of a clock cycle divided by a desired time unit. The value held by the counter does not represent a count of clock cycles, but rather a count of time units. In other aspects, a device generates fixed delays derived from a variable frequency input clock. The device includes a count circuit () and a comparator (). The number of time-units between consecutive clock edges of the input clock is stored, and the count circuit changes a current-count value by a corresponding amount, with the change being responsive to a clock edge of the input clock. The comparator () compares the current-count value to a fixed value that represents a fixed delay time.