The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Jun. 13, 2011
Jinn-shyan Wang, Chiayi, TW;
Chun-yuan Cheng, Yunlin County, TW;
Chih-chiang Liu, New Taipei, TW;
National Chung Cheng University, Chiayi County, TW;
Abstract
A clock de-skewing delay locked loop circuit is revealed. In the clock de-skewing delay locked loop circuit, a timing control circuit generates a first and a second clock signals according to an external and an internal clock signal. A clock delay line delays the first clock signal or the external clock signal to generate delay signals. A delay mirror circuit synchronizes the internal clock signal with the external clock signal. A phase adjustment circuit inverts the internal clock signal according to the phase difference. An inverting buffer circuit buffers the external clock signal or the first clock signal for adding an initial delay time so as to make a duty cycle of internal clock signal and of the external clock signal complement each other. Thus the duty cycle of the external clock signal in the proposed circuit is not necessarily 50%.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile