The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Feb. 11, 2011
Chao-yen Lin, Ruifang Township, Taipei County, TW;
Wen-chou Tsai, Taoyuan, TW;
Ming-hong Fang, Hsinchu, TW;
Jen-yen Wang, Toufen Township, Miaoli County, TW;
Chih-hao Chen, Shulin, TW;
Guo-jyun Chiou, Zhongli, TW;
Sheng-hsiang Fu, Zhongli, TW;
Chao-Yen Lin, Ruifang Township, Taipei County, TW;
Wen-Chou Tsai, Taoyuan, TW;
Ming-Hong Fang, Hsinchu, TW;
Jen-Yen Wang, Toufen Township, Miaoli County, TW;
Chih-Hao Chen, Shulin, TW;
Guo-Jyun Chiou, Zhongli, TW;
Sheng-Hsiang Fu, Zhongli, TW;
Other;
Abstract
A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.