The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2012
Filed:
Jan. 06, 2006
Limin He, Saratoga, CA (US);
So-zen Yao, Fremont, CA (US);
Wenyong Deng, San Jose, CA (US);
Jing Chen, Fremont, CA (US);
Liang-jih Chao, Fremont, CA (US);
Limin He, Saratoga, CA (US);
So-Zen Yao, Fremont, CA (US);
Wenyong Deng, San Jose, CA (US);
Jing Chen, Fremont, CA (US);
Liang-Jih Chao, Fremont, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.