The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2012

Filed:

Dec. 31, 2011
Applicants:

Christopher Wilkerson, Portland, OR (US);

Muhammad M. Khellah, Tigard, OR (US);

Vivek DE, Beaverton, OR (US);

Ming Zhang, Portland, OR (US);

Jaume Abella, Barcelona, ES;

Javier Carretero Casado, Barcelona, ES;

Pedro Chaparro Monferrer, Barcelona, ES;

Xavier Vera, Barcelona, ES;

Antonio Gonzalez, Barcelona, ES;

Inventors:

Christopher Wilkerson, Portland, OR (US);

Muhammad M. Khellah, Tigard, OR (US);

Vivek De, Beaverton, OR (US);

Ming Zhang, Portland, OR (US);

Jaume Abella, Barcelona, ES;

Javier Carretero Casado, Barcelona, ES;

Pedro Chaparro Monferrer, Barcelona, ES;

Xavier Vera, Barcelona, ES;

Antonio Gonzalez, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.


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