The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2012
Filed:
Aug. 02, 2007
Harry Chuang, Austin, TX (US);
Kong-beng Thei, Hsin-Chu, TW;
Mong Song Liang, Hsin-Chu, TW;
Sheng-chen Chung, Hsin-Chu, TW;
Chih-tsung Yao, Hsin-Chu, TW;
Jung-hui Kao, Hsin-Chu, TW;
Chung Long Cheng, Hsin-Chu, TW;
Gary Shen, Hsin-Chu, TW;
Gwan Sin Chang, Hsin-Chu, TW;
Harry Chuang, Austin, TX (US);
Kong-Beng Thei, Hsin-Chu, TW;
Mong Song Liang, Hsin-Chu, TW;
Sheng-Chen Chung, Hsin-Chu, TW;
Chih-Tsung Yao, Hsin-Chu, TW;
Jung-Hui Kao, Hsin-Chu, TW;
Chung Long Cheng, Hsin-Chu, TW;
Gary Shen, Hsin-Chu, TW;
Gwan Sin Chang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.