The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2012
Filed:
Dec. 27, 2010
Taranjit Singh Kukal, Delhi, IN;
Feras Al-hawari, Chelmsford, MA (US);
Dennis Nagle, Peabody, MA (US);
Raymond Komow, Chelmsford, MA (US);
Jilin Tan, Nashua, NH (US);
Taranjit Singh Kukal, Delhi, IN;
Feras Al-Hawari, Chelmsford, MA (US);
Dennis Nagle, Peabody, MA (US);
Raymond Komow, Chelmsford, MA (US);
Jilin Tan, Nashua, NH (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A system and method is provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.