The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2012

Filed:

Dec. 10, 2007
Applicants:

Yeon-ho Kim, Seoul, KR;

Kyeong-han Lee, Gyeonggi-do, KR;

Jong-hwa Kim, Geonggi-do, KR;

In-young Kim, Seoul, KR;

Young-joon Choi, Gyeonggi-do, KR;

Seok-cheon Kwon, Gyeonggi-do, KR;

Inventors:

Yeon-Ho Kim, Seoul, KR;

Kyeong-Han Lee, Gyeonggi-do, KR;

Jong-Hwa Kim, Geonggi-do, KR;

In-Young Kim, Seoul, KR;

Young-Joon Choi, Gyeonggi-do, KR;

Seok-Cheon Kwon, Gyeonggi-do, KR;

Assignee:

Samsung Electronics Co., Ltd., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.


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