The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2012

Filed:

Feb. 17, 2010
Applicants:

Chiung C. Lo, Campbell, CA (US);

Arkadii V. Samoilov, Saratoga, CA (US);

Reynante Alvarado, San Jose, CA (US);

Inventors:

Chiung C. Lo, Campbell, CA (US);

Arkadii V. Samoilov, Saratoga, CA (US);

Reynante Alvarado, San Jose, CA (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.


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