The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Jul. 23, 2010
Vishnu K. Khemka, Phoenix, AZ (US);
Stephen J. Cosentino, Gilbert, AZ (US);
Tahir A. Khan, Tempe, AZ (US);
Adolfo C. Reyes, Tempe, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Vishnu K. Khemka, Phoenix, AZ (US);
Stephen J. Cosentino, Gilbert, AZ (US);
Tahir A. Khan, Tempe, AZ (US);
Adolfo C. Reyes, Tempe, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An LDMOSFET transistor () is provided which includes a substrate (), an epitaxial drift region () in which a drain region () is formed, a first well region () in which a source region () is formed, a gate electrode () formed adjacent to the source region () to define a first channel region (), and a grounded substrate injection suppression guard structure that includes a patterned buried layer () in ohmic contact with an isolation well region () formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region () and from the drain region (), where the buried layer () is disposed below the first well region () but not below the drain region ().