The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Apr. 22, 2008
Teruyuki Hotta, Osaka, JP;
Shushi Morimoto, Osaka, JP;
Takahiro Ishizaki, Osaka, JP;
Hisamitsu Yamamoto, Osaka, JP;
Teruyuki Hotta, Osaka, JP;
Shushi Morimoto, Osaka, JP;
Takahiro Ishizaki, Osaka, JP;
Hisamitsu Yamamoto, Osaka, JP;
C. Uyemura & Co., Ltd., Osaka, JP;
Abstract
The present invention is directed to a method for manufacturing a printed circuit board in which a plurality of conductive layers forming a wiring pattern are laminated in the state where they are put between insulating layers, and a printed circuit board formed thereby. The printed circuit board manufacturing method for the present invention includes a step of forming a via fill () to allow electroless plating liquid to be in contact with the surface of the wiring pattern exposed to a bottom part of a via hole () formed at a insulating layer to laminate plating metallic film from the bottom part to a opening part of the via hole (), to form the via fill (), and a step of forming a wiring pattern to form electroless plating metallic film () serving as the wiring pattern onto a substrate where the via fill () is formed.