The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2012

Filed:

Dec. 22, 2005
Applicants:

Theodros Yigzaw, Sherwood, OR (US);

Geeyarpuram N. Santhanakrishnan, Hillsboro, OR (US);

Mark Rowland, Beaverton, OR (US);

Ganapati Srinivasa, Portland, OR (US);

Inventors:

Theodros Yigzaw, Sherwood, OR (US);

Geeyarpuram N. Santhanakrishnan, Hillsboro, OR (US);

Mark Rowland, Beaverton, OR (US);

Ganapati Srinivasa, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.


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