The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2012

Filed:

Dec. 30, 2009
Applicants:

Vikas Kohli, Noida, IN;

Dhamarajan Sankaran, Nodia, IN;

Steve R. Durrill, Campbell, CA (US);

Inventors:

Vikas Kohli, Noida, IN;

Dhamarajan Sankaran, Nodia, IN;

Steve R. Durrill, Campbell, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A printed circuit board (PCB) block diagram tool for block diagram level editing of a PCB design abstracted from a PCB physical layout tool is disclosed. The PCB block diagram tool includes a plurality of interface objects, a plurality of block objects and interconnect lines. The plurality of interface objects represents interfaces between components. Each of the plurality of interface objects include a plurality of signal, power and ground signal lines without defined physical assignment to pin or pad. The plurality of block objects represents a plurality of physical objects in the PCB physical layout tool. The plurality of blocks are configured to accept the plurality of interface objects. Interconnect lines connect the plurality of interface objects between the plurality of block objects.


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